IBM revealed a disruptive technological innovation by presenting the world’s first chip with a scale of less than a nanometer. This new technology can integrate almost 100 billion transistors into a component the size of a fingernail, doubling the density achieved by IBM’s own 2 nanometer chip, launched in 2021.
This significant advancement is the result of several innovations in structure and materials, including IBM’s three-dimensional nanostack architecture. The company demonstrates that continued gains in performance and energy efficiency remain viable, even with chip dimensions approaching atomic scales.
The released technical data indicates that the new chip promises a considerable leap in capacity. It is estimated to provide up to a 50% increase in performance or a 70% improvement in energy efficiency compared to IBM’s 2nm chips, boosting computing in diverse areas such as generative artificial intelligence, cloud infrastructure and next-generation electronic devices.
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Revolutionary advances in nanostack chip design
To create this first-of-its-kind component, IBM researchers developed a completely unique transistor architecture called a “nanostack.” This is the industry’s first known three-dimensional design based on nanosheets, representing a remarkable evolution of nanosheet technology, originally invented by IBM and now the industry standard.
The nanostack architecture allows you to stack and scale transistors vertically, using 3D sequential integration to accommodate a greater number of components on a single chip. Furthermore, the design allows the use of different combinations of materials in each stacked layer, optimizing the performance and energy efficiency of each transistor independently.
The viability of IBM’s nanostack architecture was confirmed through experimental validation, including ultrathin dielectric bonding in CMOS integration and demonstration of dual-channel engineering capability and functional operation of CMOS inverters with expected switching performance. Collectively, these results attest to the physical constructability and real computing support of nanostack technology.
Recent research, presented at the VLSI 2026 conference, shows that the nanostack architecture provides 40% scaling in SRAM. This feat is crucial as it frees chip designers to develop much more efficient components while meeting the high data demands of advanced artificial intelligence workloads. This movement toward the angstrom scale, which approaches the dimensions of individual atoms, is critical to overcoming previously imagined physical limits to advancing Moore’s Law, promising a new era of miniaturization in semiconductors.
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Continued leadership in semiconductor innovation at IBM
This latest innovation serves as clear proof of IBM’s continued leadership in semiconductor research and development. For decades, the company has been a global pioneer in developing chips that power diverse computing systems, from the early days of semiconductors in the 1960s to the world’s first 2-nanometer chip. IBM continues to innovate at the forefront of silicon, artificial intelligence hardware, logic and quantum processors, all designed to shape the future of computing.
The company and its collaborators conduct these projects at one of its main semiconductor research centers, located in Albany, New York. This center will soon receive a high numerical aperture extreme ultraviolet lithography (high NA EUV) tool, crucial equipment for the next phase of logic miniaturization. Developed by ASML, this technology allows the printing of circuits with ultra-precision, facilitating the creation of smaller and even more powerful chips. IBM, together with partners including Lam Research Corp., Tokyo Electron and SCREEN Semiconductor Solutions, Ltd., has collaborated to develop new high-NA EUV processes and tools, already resulting in functional devices.
Recently, IBM also communicated its plan to establish Anderon, which will be the first pure quantum foundry on the planet. Anderon, a company independent of IBM, will capitalize on IBM’s vast experience in quantum computing and semiconductors to position the United States as the leading global producer of quantum wafers.
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With nanostructure technology expected to be implemented at the sub-1 nanometer node as quickly as possible, IBM envisions a timeline to begin production within the next five years.