Japanese company Rapidus presented an innovative glass interposer prototype during Semicon Japan 2025, held at Tóquio from December 17th. Essa technology aims to reduce semiconductor production costs for artificial intelligence and position the company as a direct competitor to TSMC, a global leader in the sector. The event brought together giants such as NVIDIA, Intel and Micron, highlighting the growing interest in the advanced packaging market.
Rapidus developed the interposer using 600 millimeter glass substrates, adapting mature LCD display processing techniques for semiconductor applications. Essa approach allows for greater usable area, with gains of 30% to 100% compared to traditional silicon interposers, in addition to better electrical performance.
Glass Substrate Technology
The prototype allows yields up to 10 times higher per sheet compared to 300 millimeter round silicon wafers. Rapidus recruited experienced engineers from Japanese display manufacturers such as Sharp to overcome challenges such as material brittleness and deformation.
Pilot production began in June 2025 in a clean room at Chitose, Hokkaido. The company plans mass production from 2028, focusing on AI chips that integrate GPUs and high-bandwidth memories.
- Greater efficiency: Substrato square reduces waste.
- Lower cost: Aproveita consolidated LCD processes.
- Superior performance: Vidro offers advantageous electrical properties.
Advances in the 2nm process
Rapidus maintains an accelerated schedule for advanced nodes, with pilot production of 2nm GAA transistors already underway. In July 2025, the company confirmed electrical characteristics in prototypes in the IIM-1 line.
Partnership with IBM accelerates technology transfer for gate-all-around. Installation of ASML’s EUV equipment occurred in late 2024, enabling EUV exposure in April 2025.
The company connected more than 200 advanced equipment in June 2025 for an automated individual wafer handling system. Essa approach prioritizes accuracy and defect reduction in cutting-edge processes.
AI-powered design tools
During Semicon Japan, Rapidus launched AI-agentic tool suite for semiconductor design. Denominada Raads, the solution includes an RTL generator based on large language models and performance, power and area predictors.
The tools promise to reduce design time by up to 50% and costs by 30%. Elas will be released gradually from 2026, integrated into process design kits for 2nm.
- Raads Generator: Cria RTL code optimized from specs.
- Integration with RUMS: Conceito unified and rapid manufacturing from Rapidus.
Mass production plan
Rapidus targets 2nm mass production in 2027, with total investments projected in trillions of yen. The Japanese government has committed significant cumulative subsidies until 2027, complemented by private contributions.
The company plans second fab at Hokkaido for nodes like 1.4nm from 2029. Foco on chips for AI and high-performance computing differentiates strategy from TSMC’s broad coverage.
Government support and investments
The project receives support from large Japanese corporations, such as Toyota, Sony and SoftBank. Bancos like Mitsubishi UFJ, Sumitomo Mitsui and Mizuho prepare long-term financing.
The initiative is part of the national strategy to recover autonomy in advanced semiconductors. Hokkaido emerges as a pole, with favorable conditions such as abundant water and cold climate.
Rapidus attracts interest from US and global customers for 2nm prototypes. Colaborações international institutions, including with IBM and European institutions, strengthen development.
Advanced Packaging Strategy
The glass interposer positions the Rapidus in the production backend, a critical area for AI chiplets. Diferencia builds on TSMC’s silicon-based CoWoS and advances in parallel with Intel’s efforts on glass substrates.
The company has established packaging R&D center, Rapidus Chiplet Solutions. Protótipos accommodate larger chips, meeting the demand for powerful GPUs like those from NVIDIA.
- Competitive advantage: Maior area and lower cost per interposer.
- Applications: Montagem of graphics processors and HBM memories.
Progress on Hokkaido
The IIM-1 fab at Chitose advances rapidly since groundbreaking in 2023. State-of-the-art Equipamentos operate in single-wafer mode for real-time optimization.
The region benefits economically from the creation of qualified jobs. Parcerias with local universities train engineers to meet the demand for talent.
Rapidus adopts automation and AI in processes for efficiency. Metas include short TAT, with cycles up to 50 days versus industry standards.
The presentation at Semicon Japan reinforces Japanese ambition in cutting-edge semiconductors. Tecnologias as glass interposer and AI-powered design tools signal competitive entry into TSMC-dominated market.
The company balances 2nm front-end with innovations in post-processing. Investimentos continued global partnerships support trajectory to commercial production.
Perspectives for the AI market
Demand for advanced packaging grows with chiplet architectures. The glass prototype meets dense integration needs for AI servers.
Rapidus seeks to diversify the global supply chain, reducing dependence on a few manufacturers. Avanços Japanese contribute to resilience in critical semiconductors.
