The semiconductor industry has just witnessed a significant advancement with the unveiling of the first chip with sub-1 nanometer technology by IBM. This achievement represents a crucial milestone for an industry that has been dealing with the challenges inherent in the physical limits of the miniaturization of electronic components. Chips are fundamental parts, present in computers, household appliances, communication devices, transport systems and throughout modern vital infrastructure.
IBM’s unprecedented component, measuring less than 1 nanometer, can integrate around 100 billion transistors in a tiny space, equivalent to the size of a fingernail. This density is almost double that achieved by the 2 nanometer chip, which IBM itself had presented in 2021. The feat is the result of a series of innovations in materials and structures, such as the three-dimensional nanostack architecture developed by the company, proving that it is possible to continue improving performance and efficiency, even when chip dimensions approach the atomic scale.
Released technical reports indicate that the new microprocessor will deliver a significant increase in capacity. It is estimated up to 50% more performance or 70% greater energy efficiency compared to IBM’s 2 nanometer chips. This means a fundamental boost for advanced applications such as generative artificial intelligence, cloud computing infrastructures and the next generation of consumer electronics, reinforcing the country’s position in the global technology race and the direct impact on the speed of innovations that shape our daily lives.
According to Jay Gambetta, director of research at IBM, this latest advance in the field of chips represents a historic feat for computing. He highlighted that technology now transcends the nanometer era, entering the atomic scale. Gambetta explained that, with the new nanostack architecture, the company is not limited to reducing the size of the transistors, but rather rethinking the construction of the chips to ensure greater power and energy efficiency. The executive also emphasized that this innovation is a pioneer in the industry, continuing IBM’s tradition of leading cutting-edge technologies and paving the way for the future of computing.
How innovative nanostack architecture is redefining chip design
To realize this technological advancement, IBM scientists created a completely redesigned transistor architecture known as a “nanostack.” This is the first three-dimensional nanosheet design released in the industry. The nanostack approach constitutes a considerable leap forward from existing nanosheet technology, which was already the cutting-edge standard and was also an IBM invention. The nanostack design organizes transistors into vertical stacks, using 3D sequential integration to house a greater number of components in the same space. Furthermore, this structure allows the application of different materials in each layer, individually optimizing the performance and energy efficiency of each transistor.
Experimental validation of IBM’s nanostack architecture occurred through ultrathin dielectric bonding in CMOS integration. This included demonstrating dual-channel engineering capability and effective operation of CMOS inverters, achieving anticipated switching performance. In their entirety, these tests ensure that nanostack technology is viable for physical construction and capable of supporting computing operations in real-world scenarios.
Additionally, a recent study presented at VLSI 2026 showed that the nanostack architecture allows for a 40% increase in SRAM scaling. This improvement gives chip developers the freedom to design significantly more efficient components. At the same time, it meets the high data bandwidth requirements crucial for advanced artificial intelligence workloads.
Thanks to this revolutionary structure, logic technology can now extend beyond the 1 nanometer level for the first time. It ushers in the era of angstrom-scale miniaturization, where measurements approach the dimensions of isolated atoms. Although transistor nodes currently designate a manufacturing technology generation rather than a precise physical dimension, IBM’s breakthrough of 0.7 nanometers, equivalent to 7 angstroms, proves the feasibility of continued miniaturization. With the introduction of the new nanostack architecture, IBM anticipates a future of at least a decade of advances in semiconductor miniaturization.
This innovation reaffirms IBM’s leadership position in semiconductor research and development. For several decades, the company has been a global pioneer in developing chips that power computing systems. Its trajectory includes milestones such as the first semiconductors in the 1960s and the 2 nanometer chip. IBM remains at the forefront, driving innovation in silicon, artificial intelligence hardware, logic and quantum processors, aiming to shape the future of computing.
This work is conducted by IBM and its collaborators in Albany, New York, one of the main centers of semiconductor research. This center will soon receive a high numerical aperture extreme ultraviolet lithography (high NA EUV) machine, a vital piece of equipment for future logic miniaturization. Developed by ASML, this technology makes it possible to print circuits with unparalleled precision, facilitating the creation of smaller, more powerful chips. IBM, in partnership with companies including Lam Research Corp., Tokyo Electron and SCREEN Semiconductor Solutions, Ltd., has collaborated to develop new high NA EUV processes and tools that have already resulted in operational devices.
IBM recently unveiled plans to create Anderon, which will be the first specialized quantum foundry globally. Anderon, operating independently from IBM, will capitalize on the company’s expertise in quantum computing and semiconductors. The objective is to strengthen the United States’ position as one of the world’s leading producers of quantum wafers.
The prediction is that nanostructure technology will be implemented at the sub-1 nanometer node as soon as possible. IBM projects that large-scale production could be a reality in the next five years, consolidating the next phase of technological evolution.
