AMD’s new Zen 6 architecture raises desktop standards with 24-core Olympic Ridge chips

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Ryzen Zen Foto: Ryzen Zen - Mino Surkala/ Shutterstock.com

The Advanced Micro Devices sets a new benchmark for computational processing by significantly expanding the capacity of its consumer-facing components. The next generation of processors, known internally by the codename Olympic Ridge, breaks the previous technical barrier and introduces models that reach twenty-four physical processing units on the conventional platform, surpassing the limit of sixteen cores established in past generations.

Engineering details and hardware configurations

This technical evolution is enabled by the introduction of the Zen 6 architecture, which uses TSMC’s 2-nanometer manufacturing process to optimize energy efficiency and transistor density. The internal structure of the components was redesigned to accommodate up to twelve cores per processing complex, technically called CCDs. Isso enables unprecedented scalability, offering robust configurations to the market that include 24-core variants for maximum productivity and 20-core options aimed at lightweight workstations.

AMD
AMD-X

The flexibility of the new line extends to cover different performance ranges, filling market gaps with intermediate models with 10 and 12 cores, in addition to the traditional 6 and 8 core options for the entry and gaming segment. The increase in L3 cache memory is also an engineering focal point, with each complex of cores accessing up to 48 MB, resulting in a total of 96 MB of cache on high-end models, ensuring lower latency in intensive computational tasks.

Compatibility and advancements on the AM5 platform

One of the main attractions for current users is the maintenance of support for the AM5 socket, guaranteeing the longevity of motherboards already available on the market through simple firmware updates. Além of the raw increment in core count, the new architecture brings substantial improvements in instructions per cycle and improved native support for AVX-512 instruction sets, aiming to accelerate workloads related to artificial intelligence and professional video editing.

These components are expected to hit shelves in the second half of the year, consolidating the manufacturer’s strategy of offering server-level performance in home computers. The inclusion of 3D memory stacking technologies in specific models is also confirmed in the launch roadmap, promising additional performance gains for the electronic games segment and applications sensitive to memory access speed.

Luís Henrique Costa é jornalista formado pela FMU, editor-chefe e fundador do Mix Vale, portal de notícias em atividade desde 2013. Responde pela direção editorial do veículo, que cobre Brasil e mundo em economia, benefícios sociais, esportes, tecnologia, ciência e entretenimento. Atua na área há mais de 15 anos e lidera uma equipe de cerca de 15 colaboradores.

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